1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, a semiconductor memory device having a data readout scheme based on a time-shared sensing scheme for reading out data of plural bits stored in a single memory cell in a time-shared manner.
2. Description of the Related Art
In general, a readout circuit of a semiconductor memory device supplies a current to a memory cell storing information, compares the current flowing through the memory cell (cell current) with a reference current, and determines whether the cell current is larger or smaller than the reference current, thereby taking out the information written in the memory cell. As such, a scheme for taking out information by comparison of the cell current is referred to as a current sensing scheme.
For example, in a so-called binary type semiconductor memory device wherein information of one bit is stored in one memory cell, as shown in FIG. 5B, there are prepared two states: a state where a cell current is large (corresponding to information “1”) and a state where a cell current is small (corresponding to information “0”) and a value of a reference current is set to an intermediate value between the two states; thus, it is possible to read out information of one bit. In practice, the semiconductor memory device is constructed so as to apply current-voltage conversion to the cell current and the reference current, respectively, to compare the respective potentials.
In recent years, in order to increase a memory capacity and reduce manufacturing cost of a semiconductor chip, there has been proposed a multilevel type semiconductor memory device capable of storing information of at least two bits in one memory cell.
In the multilevel type semiconductor memory device for storing information of two bits in one memory cell, for example, as shown in FIG. 5A, there are prepared four kinds of states that can be taken by a cell current to set three kinds of reference current values “H”, “M” and “L” between the respective data regions, thereby making it possible to read out information of two bits. In the case of storing information of “n” bits in one memory cell in such a multilevel type semiconductor memory device, it is necessary to prepare 2n kinds of states that can be taken by the cell current and set (2n−1) kinds of reference current values.
At present, upon reading out data from a multilevel type semiconductor memory device, several schemes are proposed. As one of such schemes, there can be mentioned a time-shared sensing scheme for performing sequential current comparison in a time-shared manner such as to perform a single kind of current comparison at a time and, depending on the result thereof, to perform current comparison on other state.
Hereinafter, as one example of the time-shared sensing scheme, description will be given of operations upon reading out data of 2-bit/cell shown in FIG. 5A with reference to FIGS. 3 and 4.
FIG. 3 is a block diagram showing an example of constitution of the readout circuit of the time-shared sensing scheme in the conventional multilevel type semiconductor memory device. This readout circuit using the time-shared sensing scheme includes a current load circuit 1, a current load circuit 2, a sense amplifier 3, a first sensed data latch circuit 4, a second sensed data latch circuit 5, a control circuit 6, a first output buffer circuit 7, a second output buffer circuit 8, reference current resources 10 to 12, a selection circuit 15, and the like.
In FIG. 3, the readout circuit using the time-shared sensing scheme includes the current load circuit 1 for obtaining a readout current (cell current) by giving a voltage to a drain (drain electrode) of a selected cell 9 which is a memory cell from which data is read out, and the current load circuit 2 for obtaining a reference current. Between the drain of the selected cell 9 and the current load circuit 1, there is connected a sensing line 13. To the current load circuit 2, there is connected a reference line 14. The sensing line 13 and the reference line 14 are connected with an input part of the sense amplifier 3 for outputting by amplification the potential difference between the sensing line 13 and the reference line 14.
To an output node Vsa of the sense amplifier 3, there are connected the first sensed data latch circuit 4 for latching a first time sensing result and the second sensed data latch circuit 5 for latching a second time sensing result. Further, the first sensed data latch circuit 4 and the second sensed data latch circuit 5 are connected with the control circuit 6, and receive a first sensed data latch control signal Vsal1 and a second sensed data latch control signal Vsal2, respectively, for controlling the timing of latching the data from the control circuit 6.
The first sensed data latch circuit 4 is connected with the selection circuit 15, and first sensed data Vout1 is outputted from the first sensed data latch circuit 4. The selection circuit 15 is connected to the reference current resources 10 to 12 and the reference line 14. At the time of the first sensing operation, the reference line 14 is connected to the reference current resource 10 by the selection circuit 15. At the time of the second sensing operation, the reference line 14 is connected by switching to the reference current resources 11 and 12 by the selection circuit 15 based on the first sensed data Vout1.
Further, connection is made between the first sensed data latch circuit 4 and the first output buffer circuit 7, and the first sensed data Vout1 outputted from the first sensed data latch circuit 4 is inputted to the first output buffer circuit 7. Then, connection is made between the second sensed data latch circuit 5 and the second output buffer circuit 8, and second sensed data Vout2 outputted from the second sensed data latch circuit 5 is inputted to the second output buffer circuit 8.
Besides, the control circuit 6 is connected to both the first output buffer circuit 7 and the second output buffer circuit 8 via a control signal line 16. A sensed data output control signal Voe for controlling the operation timing from the control circuit 6 is inputted simultaneously to both the first output buffer circuit 7 and the second output buffer circuit 8.
Then, the sensed data are outputted from the first output buffer circuit 7 and the second output buffer circuit 8 to a first output pad Vpad1 and a second output pad Vpad2, respectively.
In the readout circuit using the time-shared sensing scheme, constituted as described above, data is read out from the selected cell 9 as follows. FIG. 4 is a timing chart of principal parts of FIG. 3 in the conventional readout operation. Herein, description will be given taking an example of a case where the selected cell stores data of “01”. Also, the initial value of the output node Vsa of the sense amplifier 3 is assumed to be “1”, and the initial values of the first sensed data latch circuit 4 and second sensed data latch circuit 5 are assumed to be “1” and “0”, respectively.
First, by applying appropriate voltages to a gate (gate electrode) and a drain (drain electrode) of the selected cell 9, a cell current flowing through the selected cell 9 is generated. By the mutual dragging with the current load circuit 1 (voltage drop by the current load circuit 1), a sensing voltage is generated on the sensing line 13.
Similarly to the above, due to the mutual dragging between the reference current flowing through the reference current resource 10 selected by the selection circuit 15 and the current load circuit 2, a reference voltage is generated on the reference line 14.
The potential difference between the sensing voltage and reference voltage thus generated is outputted by amplification to the output node Vsa of the sense amplifier 3 (time t1). This operation is referred to as a first sensing operation. Herein, the reference current resource 10 selected by the selection circuit 15 at the time of the first sensing operation for obtaining the first sensed data Vout1 is used for obtaining a reference current value “M” between the data regions “01” and “10” out of the three reference currents shown in FIG. 5A. Ordinarily, as the reference current resources 10 to 12, there is used a reference cell having the same structure and same characteristics as those of the memory cell in which a threshold value is strictly adjusted so as to obtain an appropriate reference current. In this example, since the selected cell 9 stores the data of “01”, “0” is outputted to the output node Vsa of the sense amplifier 3.
Then, the first sensed data latch control signal Vsal1 outputted from the control circuit 6 transits from “1” to “0” (time t2), and the first sensed data Vout1 is renewed to become Vout1=Vsa=“0” and is stored in the first sensed data latch circuit 4 (time t3).
Next, based on the first sensed data Vout1 stored in the first sensed data latch circuit 4, the selection circuit 15 switches the reference current resource 10 to the reference current resource 11 or the reference current resource 12. At this time, in the case that the first sensed data Vout1 stored in the first sensed data latch circuit 4 is “0”, switching is made to the reference current resource 11, and in case that the first sensed data Vout1 is “1”, switching is made to the reference current resource 12. Herein, the reference current resource 11 is used for obtaining the reference current value “H” between the data regions “00” and “01” out of the three reference currents shown in FIG. 5A, and the reference current resource 12 is used for obtaining the reference current value “L” between the data regions “10” and “11”. In this case, since the first sensed data Vout1 is “0”, switching is made to the reference current resource 11.
Thereafter, a second sensing operation is performed in the same manner as the first sensing operation, so that a signal based on the potential difference between the sensing voltage and the reference potential of the resource 11 is amplified by the sense amplifier 3 and outputted to the output node Vsa of the sense amplifier (time t5). In this example, since the selected cell 9 stores the data of “01”, “1” is outputted to the output node Vsa of the sense amplifier 3.
Then, the second sensed data latch control signal Vsal2 outputted from the control circuit 6 transits from “1” to “0” (time t6), and the second sensed data Vout2 is renewed to become Vout2=Vsa=“1” and is stored in the second sensed data latch circuit 5 (time t7). As described above, it is possible to obtain data of two bits stored in one memory cell 9 as the first sensed data Vout1 and the second sensed data Vout2.
Finally, the sensed data output control signals Voe inputted simultaneously to both the first output buffer circuit 7 and the second output buffer circuit 8 from the control circuit 6 transit from “0” to “1” (time t8), the first output buffer circuit 7 and the second output buffer circuit 8 are simultaneously activated, and the first sensed data Vout1=“0” and the second sensed data Vout2=“1” are outputted to the first output pad Vpad1 and the second output pad Vpad2, respectively.
FIG. 6 shows an example of constitution of the first output buffer circuit 7 and second output buffer circuit 8. The output buffer circuit includes an inverter 61 with an enable signal, to which sensing data Vout is inputted, a latch circuit 62, an output buffer 63, and the like. The inverter 61 with an enable signal acts as an inverter only when the sensed data output control signal Voe is “1”, and enters a state of output high impedance when the signal Voe is “0”. The output of the inverter 61 with an enable signal is connected to the latch circuit 62 by which the data is stably held, and the output buffer 63 outputs the data to the output pad Vpad. Further, as a Pch transistor 64 and an Nch transistor 65 of the output buffer 63, very large-sized transistors are used because of a necessity to output the data contained in a chip externally at high speed through the output pad Vpad.
Herein, when the sensed data output control signal Voe transits from “0” to “1” and the output buffer circuit is activated, if data Vbufb held by the latch circuit 62 differs from the sensed data Vout in this time, the data Vbufb held in the latch circuit 62 and inverse data Vbuf thereof are renewed, respectively. At this time, there arises a timing where the Pch transistor 64 and the Nch transistor 65 are simultaneously switched on; thus, a through current flows from a power source Vcc to a ground GND.
There is also a requirement in recent years to make the output multi-bits in a semiconductor memory device, and, in order to make the output multi-bits, it is necessary to provide an output buffer circuit for each bit. However, the noise of the output buffer 63 is increased as the amount of through current is larger, i.e., the larger the number of output buffers 63 operating simultaneously is, and the larger the size of the transistor of the output buffer 63 is. There is a problem that, in the event of the simultaneous switching of many of these output buffers 63, large noise generates due to the instantaneous flowing of large through current to induce erroneous operations to the peripheral apparatuses and own circuits.
It is possible to suppress through currents and reduce noise by lowering the current drivability of the transistors of the output buffers 63. Besides, there is disclosed a method for displacing timings of output for each bit by providing a delay circuit, thereby displacing peak timings of through currents flowing instantaneously and reducing noise (see, for example, JP-A 2003-8424, JP-A05-100778 (1993)).
However, lowering the current drivability of the transistors of the output buffers 63 induces retardation of the transition rate of the output voltage, i.e., retardation of the readout rate. Besides, when the noise reduction method disclosed in the aforementioned publications is applied to a semiconductor memory device, in consequence of the displacement of the output timings, readout rate is delayed by the displaced time. As such, in the case of using any of the aforementioned methods for a semiconductor memory device, there arises a problem of exerting an adverse effect to the readout rate.